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a ad8565/ad8566/ad8567 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2004 analog devices, inc. all rights reserved. 16 v rail-to-rail operational amplifiers pin configurations features single-supply operation: 4.5 v to 16 v input capability beyond the rails rail-to-rail output swing continuous output current: 35 ma peak output current: 250 ma offset voltage: 10 mv slew rate: 6 v/ s unity gain stable with large capacitive loads supply current: 700 a per amplifier applications lcd reference drivers portable electronics communications equipment general description the ad8565, ad8566, and ad8567 are low cost, single-supply rail-to-rail input and output operational amplifiers optimized for lcd monitor applications. they are built on an advanced high voltage cbcmos process. the ad8565 contains a single amplifier, the ad8566 has two amplifiers, and the ad8567 has four amplifiers. these lcd op amps have high slew rates, 35 ma continuous output drive, 250 ma peak output drive, and high capacitive load drive capability. they have a wide supply range and offset volt- ages below 10 mv. the ad8565, ad8566, and ad8567 are ideal for lcd grayscale reference buffer and v com applications. the ad8565, ad8566, and ad8567 are specified over the C 40 c to +85 c temperature range. the ad8565 single is available in a 5-lead sc70 package. the ad8566 dual is available in an 8-lead msop package. the ad8567 quad is available in 14-lead tssop and 16-lead lfcsp packages. 5-lead sc70 (ks suffix) 1 2 3 5 4 ?n +in v out ad8565 v+ 14-lead tssop (ru suffix) out b +in b ?n b v+ ?n a +in a out a 78 510 69 4 11 213 3 12 1 14 out c +in c ?n c v ?n d +in d out d ad8567 16-lead lfcsp (cp suffix) top view 16 5 13 8 9 12 1 4 14 15 2 3 7 6 11 10 ?n d +in d v +in c ?n a +in a v+ +in b nc out a out d nc ?n b out b out c ?n c ad8567 nc = no connect 8-lead msop (rm suffix) 45 2 7 36 1 8 out a ?n a +in a v v+ out b ?n b +in b ad8566
e2e rev. c ad8565/ad8566/ad8567especifications electrical characteristics parameter symbol conditions min typ max unit input characteristics offset voltage v os 210 mv offset voltage drift v os / t ? 40 c t a +85 c5 v/ c input bias current i b 80 600 na ? 40 c t a +85 c 800 na input offset current i os 180 na ? 40 c t a +85 c 130 na input voltage range common-mode input ? 0.5 v s + 0.5 v common-mode rejection ratio cmrr v cm = 0 to v s , ? 40 c t a +85 c5495 db large signal voltage gain avo r l = 10 k , v o = 0.5 v to (v s ? 0.5 v) 3 10 v/mv input impedance z in 400 k input capacitance c in 1pf output characteristics output voltage high v oh i l = 100 av s ? 0.005 v v s = 16 v, i l = 5 ma 15.85 15.95 v ? 40 c t a +85 c 15.75 v v s = 4.5 v, i l = 5 ma 4.2 4.38 v ? 40 c t a +85 c 4.1 v output voltage low v ol i l = 100 a5mv v s = 16 v, i l = 5 ma 42 150 mv ? 40 c t a +85 c 250 mv v s = 4.5 v, i l = 5 ma 95 300 mv ? 40 c t a +85 c 400 mv continuous output current i out 35 ma peak output current i pk v s = 16 v 250 ma power supply supply voltage v s 4.5 16 v power supply rejection ratio psrr v s = 4 v to 17 v, ? 40 c t a +85 c7090 db supply current/amplifier i sy v o = v s /2, no load 700 850 a ? 40 c t a +85 c1ma dynamic performance slew rate sr r l = 10 k , c l = 200 pf 4 6 v/ s gain bandwidth product gbp r l = 10 k , c l = 10 pf 5 mhz phase margin ? or l = 10 k , c l = 10 pf 65 degrees channel separation 75 db noise performance voltage noise density e n f = 1 khz 26 nv/ hz hz hz hz hz
ad8565/ad8566/ad8567 e3e rev. c absolute maximum ratings * supply voltage (v s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v input voltage . . . . . . . . . . . . . . . . . . . . . ? 0.5 v to v s + 0.5 v differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . v s storage temperature range . . . . . . . . . . . . ? 65 c to +150 c operating temperature range . . . . . . . . . . . ? 40 c to +85 c junction temperature range . . . . . . . . . . . . ? 65 c to +150 c lead temperature range (soldering, 60 sec) . . . . . . . . 300 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ordering guide temperature package model range package description option branding ad8565aks-r2 ? 40 c to +85 c 5-lead thin shrink small outline transistor package ks-5 asa ad8565aks-reel7 ? 40 c to +85 c 5-lead thin shrink small outline transistor package ks-5 asa ad8565aksz-reel7 * ? 40 c to +85 c 5-lead thin shrink small outline transistor package ks-5 asa ad8566arm-r2 ? 40 c to +85 c 8-lead micro small outline package rm-8 ata ad8566arm-reel ? 40 c to +85 c 8-lead micro small outline package rm-8 ata ad8566armz-reel * ? 40 c to +85 c 8-lead micro small outline package rm-8 ata ad8567aru ? 40 c to +85 c 14-lead thin shrink small outline package ru-14 ad8567aru-reel ? 40 c to +85 c 14-lead thin shrink small outline package ru-14 ad8567aruz * ? 40 c to +85 c 14-lead thin shrink small outline package ru-14 ad8567aruz-reel * ? 40 c to +85 c 14-lead thin shrink small outline package ru-14 AD8567ACP-R2 ? 40 c to +85 c 16-lead lead frame chip scale package cp-16 ad8567acp-reel ? 40 c to +85 c 16-lead lead frame chip scale package cp-16 ad8567acp-reel7 ? 40 c to +85 c 16-lead lead frame chip scale package cp-16 ad8567acpz-reel * ? 40 c to +85 c 16-lead lead frame chip scale package cp-16 ad8567acpz-reel7 * ? 40 c to +85 c 16-lead lead frame chip scale package cp-16 * z = pb-free part. package type ja 1 jc unit 5-lead sc70 (ks) 376 126 c/w 8-lead msop (rm) 210 45 c/w 14-lead tssop (ru) 180 35 c/w 16-lead lfcsp (cp) 38 2 30 2 c/w notes 1 ja is specified for worst-case conditions, i.e., ja is specified for a device soldered onto a circuit board for surface-mount packages. 2 dap is soldered down to pcb. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8565/ad8566/ad8567 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
ad8565/ad8566/ad8567 e4e rev. c etypical performance characteristics temperature ( c) 0 0.25 1.50 40 input offset voltage (mv) 25 85 0.50 0.75 1.00 1.25 v cm = v s /2 v s = 16v v s = 4.5v tpc 1. input offset voltage vs. temperature frequency (hz) 10 1 0.1 10 10k 100 1k 4.5v v s 16v t a = 25 c current noise density (pa hz) tpc 2. current noise density vs. frequency frequency (1 s/div) time (50mv/div) v s = 16v r l = 10k c l = 100pf a v = +1 t a = 25 c tpc 3. small signal transient response voltage noise density (nv hz) frequency (hz) 1000 100 1 10 10k 100 1k 4.5v v s 16v t a = 25 c 10 tpc 4. voltage noise density vs. frequency supply voltage (v) 1.0 0.8 0 018 2 supply current/amplifier (ma) 46810 12 14 16 0.6 0.4 0.2 v o = v s /2 a v = +1 t a = 25 c tpc 5. supply current/amplifier vs. supply voltage temperature ( c) 0.80 0.75 0.50 40 supply current/amplifier (ma) 25 85 0.70 0.65 0.60 0.55 v cm = v s /2 v s = 16v v s = 4.5v tpc 6. supply current/amplifier vs. temperature
ad8565/ad8566/ad8567 e5e rev. c load capacitance (pf) 100 90 0 10 1k 100 overshoot (%) 80 70 60 50 40 30 20 10 v s = 16v v in = 100mv p-p r l = 10k a v = +1 t a = 25 c eos +os tpc 7. small signal overshoot vs. load capacitance frequency (hz) output swing (v p-p) 0 100 10 1k 10k 100k 1m 10m 2 4 6 8 10 12 14 16 18 v s = 16v a v = +1 r l = 10k distortion < 1% t a = 25 c tpc 8. closed-loop output swing vs. frequency frequency (hz) closed-loop gain (db) 100 10 1k 10k 100k 1m 10m 10 20 30 40 50 4.5v v s 16v r l = 10k c l = 40pf t a = 25 c 60 0 a vcl = e100 a vcl = e10 a vcl = +1 tpc 9. closed-loop gain vs. frequency 1k 100m 10k gain (db) 100k 1m 10m 100 80 60 40 20 frequency (hz) 45 90 135 180 0 225 270 phase shift (degrees) v s = 16v r l = 10k c l = 40pf t a = 25 c 0 tpc 10. open-loop gain and phase shift vs. frequency load current (ma) 10 0.1 0.001 100 0.01 0.1 1 10 1 100 v s = 4.5v 1k t a = 25 c v s = 16v output voltage (mv) tpc 11. output voltage to supply rail vs. load current temperature ( c) 150 40 output voltage (mv) 25 85 i sink = 5ma v s = 16v v s = 4.5v 135 120 105 90 75 60 45 30 15 0 tpc 12. output voltage swing to rail vs. temperature
ad8565/ad8566/ad8567 e6e rev. c temperature ( c) 150 40 output voltage (mv) 25 85 i source = 5ma v s = 16v v s = 4.5v 135 120 105 90 75 60 45 30 15 0 tpc 13. output voltage swing to rail vs. temperature frequency (hz) 100 10m 1k impedance ( ) 10k 100k 1m 500 450 0 400 350 300 250 200 150 100 50 a v = +1 t a = 25 c v s = 16v v s = 4.5v tpc 14. closed-loop output impedance vs. frequency frequency (hz) cmrr (db) 100 10 1k 10k 100k 1m 10m 20 40 60 80 100 v s = 16v t a = 25 c 120 0 140 tpc 15. common-mode rejection ratio vs. frequency frequency (hz) 100 10m 1k power supply rejection ratio (db) 10k 100k 1m 160 140 40 120 100 80 60 40 20 0 20 v s = 16v t a = 25 c + psrr epsrr tpc 16. power supply rejection ratio vs. frequency time (40 s/div) vo lta ge (3v/div) v s = 16v r l = 10k a v = +1 t a = 25 c tpc 17. no phase reversal input offset voltage (mv) 10 10 8 6 4 2 02 468 1.8k 1.6k 0 qu antity (amplifiers) 800 600 400 200 1.2k 1.0k 1.4k v s = 16v t a = 25 c tpc 18. input offset voltage distribution
ad8565/ad8566/ad8567 e7e rev. c temperature ( c) e5 e40 input offset current (na) 25 85 e1 e2 e3 e4 v s = 16v v s = 4.5v 5 1 0 3 2 4 tpc 19. input offset current vs. temperature temperature ( c) e350 e40 input bias current (na) 25 85 e150 e200 e250 e300 v s = 16v v s = 4.5v 0 e50 e100 v cm = v s /2 tpc 20. input bias current vs. temperature 16v crosstalk (db) e20 e40 e180 e60 e80 e160 e100 e120 e140 4.5v frequency (hz) 50 1k 60k 10k 100 tpc 21. channel a vs. channel b crosstalk common-mode voltage (v) 7 0 016 2 b andwidth (mhz) 46810 12 14 6 4 3 2 1 5 v s = 16v a v = +1 r l = x t a = 25 c tpc 22. frequency vs. common-mode voltage (v s = 16 v) common-mode voltage (v) 6 5 0 05 1 b andwidth (mhz) 234 4 3 2 1 v s = 5v a v = +1 r l = 10k t a = 25 c tpc 23. frequency vs. common-mode voltage (v s = 5.0 v)
ad8565/ad8566/ad8567 e8e rev. c applications theory of operation the ad856x family is designed to drive large capacitive loads in lcd applications. it has high output current drive, rail-to-rail input/output operation, and is powered from a single 16 v supply. it is also intended for other applications where low distortion and high output current drive are needed. f igure 1 illustrates a simplified equivalent circuit for the ad856x. t he r ail-to-rail bipolar input stage is composed of two pnp differential pairs, q4 to q5 and q10 to q11, operating in series with diode pro tection networks, d1 to d2. diode network d1 to d2 serves as protection against large transients for q4 to q5 to ac commodate rail-to-rail input swing. d5 to d6 protect q10 to q11 against zenering. in normal operation, q10 to q11 are off and their input stage is buffered from the operational amplifier inputs by q6 to d3 and q8 to d4. opera- tion of the input stage is best understood as a function of applied common-mode voltage: w hen the inputs of the ad856x are biased midway between the supplies, the differential signal path gain is controlled by resistive loads (via r9, r10) q4 to q5. as the input common-mode level is reduced toward the negative supply (v neg or gnd), the input transistor current sources, i1 and i2, are forced into saturation, thereby forcing the q6 to d3 and q8 to d4 networks into cutoff. however, q4 to q5 remain active, providing input stage gain. inversely, when common-mode input voltage is increased toward the positive supply, q4 to q5 are driven into cutoff, q3 is driven into saturation, and q4 becomes active, providing bias to the q10 to q11 differential pair. the point at which q10 to q11 differential pair becomes active is approximately equal to (v pos ? 1 v). r1 r3 r4 d1 d2 q4 q3 bias line ve d3 d4 q5 q4 r5 r6 q10 q11 c1 c2 d5 d6 q8 q6 r9 r10 folded cascade v+ i1 i2 v neg v pos figure 1. ad856x equivalent input circuit the benefit of this type of input stage is low bias current. the input bias current is the sum of base currents of q4 to q5 and q6 to q8 over the range from (v neg + 1 v) to (v pos ? 1 v). out- side of this range, input bias current is dominated by the sum of base currents of q10 to q11 for input signals close to v neg and of q6 to q8 (q10 to q11) for signals close to v pos . from this type of design, the input bias current of ad856x not only exhibits different amplitude but also exhibits different polarities. figure 2 provides the characteristics of the input bias current versus the common-mode voltage. it is important to keep in mind that the source impedances driving the ad856x inputs are balanced for optimum dc and ac performance. input common-mode voltage (v) 1,000 e1,000 016 2 input bias current (na) 468101 214 800 200 e200 e600 e800 600 400 0 e400 v s = 16v t a = 25 c figure 2. ad856x input bias current vs. common-mode voltage in order to achieve rail-to-rail output performance, the ad856x design uses a complementary common-source (or gmrl) output. this configuration allows output voltages to approach the power supply rails, particularly if the output transistors are allowed to enter the triode region on extremes of signal swing, which are limited by v gs , the transistor sizes, and output load current. also, this type of output stage exhibits voltage gain in an open-loop gain configuration. the amount of gain depends on the total load resistance at the output of the ad856x. input overvoltage protection as with any semiconductor device, whenever the input exceeds either supply voltages, attention needs to be paid to the input overvoltage characteristics. as an overvoltage occurs, the amplifier could be damaged, depending on the voltage level and the magnitude of the fault current. when the input voltage exceeds either supply by more than 0.6 v, internal pn junctions allow current to flow from the input to the supplies. this input current is not inherently damaging to the device as long as it is limited to 5 ma or less. if a condition exists using the ad856x where the input exceeds the supply more than 0.6 v, an external series resistor should be added. the size of the resis- tor can be calculated by using the maximum overvoltage divided by 5 ma. this resistance should be placed in series with either input exposed to an overvoltage.
ad8565/ad8566/ad8567 e9e rev. c output phase reversal the ad856x family is immune to phase reversal. although the d evice ? s output will not change phase, large currents due to input overvoltage could damage the device. in applications where the possibility of an input voltage exceeding the supply voltage exists, overvoltage protection should be used as described in the previous section. power dissipation the maximum allowable internal junction temperature of 150 c limits the ad856x family ? s maximum power dissipation of ad856x devices. as the ambient temperature increases, the maximum power dissipated by ad856x devices must decrease linearly to maintain the maxi mum junction temperature. if this maximum jun ction tem perature is exceeded momentarily, the device will still operate properly once the junction temperature is reduced below 150 c. if the maximum junction temperature is exceeded for an extended period of time, overheating could lead to permanent damage of the device. the maximum safe junction temperature, t j max , is 150 c. using the following formula, we can obtain the maximum power that an ad856x device can safely dissipate as a function of temperature: p diss = t j max ? t a / j a where: p diss = the ad856x power dissipation. t j max = the ad856x maximum allowable junction temp erature (150 c). t a = the ambient temperature of the circuit. j a = the ad856x package thermal resistance, junction-to-ambient. the power dissipated by the device can be calculated as p diss = ( v s ? v out ) i load where: v s = the supply voltage. v out = the output voltage. i load = the output load current. figure 3 shows the maximum power dissipation versus temperature. to achieve proper operation, use the previous equation to calculate p diss for a specific package at any given temperature or use the figure below. ambient temperature ( c) 1.25 0.75 0 e35 maximum power dissipation ( w) 0.50 0.25 14-lead soic 5-lead sot-23 8-lead msop 14-lead tssop 1.00 e15 5 25 4 56585 figure 3. maximum power dissipation vs. temperature for 5-, 8-, and 14-lead packages total harmonic distortion + noise (thd+n) the ad856x family features low total harmonic distortion. figure 4 shows a graph of thd+n versus frequency. the thd+n for the ad856x over the entire supply range is below 0.008%. when the device is powered from a 16 v supply, the thd+n stays below 0.003%. figure 4 shows the ad8566 in a unity noninverting configuration. frequency (hz) 20 30k thd+n (%) 100 1k 10k 10 1 0.01 0.1 v s = 2.5v v s = 8v figure 4. thd+n vs. frequency graph short-circuit output conditions the ad856x family does not have internal short-circuit protection circuitry. as a precautionary measure, it is recommended not to short the output directly to the positive power supply or to ground. it is not recommended to operate the ad856x with more than 35 ma of continuous output current. the output current can be limited by placing a series resistor at the output of the amplifier whose value can be derived using the following equation: r v x s 35 ma for a 5 v single-supply operation, r x should have a minimum value of 143 . lcd panel applications the ad856x amplifier is designed for lcd panel applications or applications where large capacitive load drive is required. it can instantaneously source/sink greater than 250 ma of current. at unity gain, it can drive 1 f without compensation. this makes the ad856x ideal for lcd v com driver applications. to evaluate the performance of the ad856x family, a test circuit was developed to simulate the v com driver application for an lcd panel.
ad8565/ad8566/ad8567 e10e rev. c figure 5 shows the test circuit. series capacitors and resistors connected to the output of the op amp represent the load of the lcd panel. the 300 and 3 k feedback resistors are used to improve settling time. this test circuit simulates the worst-case scenario for a v com . it drives a represented load that is connected to a signal switched symmetrically around v com . figure 6 displays a scope photo of the instantaneous output peak current capability of the ad856x family. input 0v to 8v square wave with 15.6 s pulse width 300 3k 10 10 10 10 10nf 10nf 10nf 10nf measure current 4v 8v 10 e20 figure 5. v com test circuit with supply voltage at 16 v 10 0% 100 90 time (2 s/div) ch 1 = 5v/div ch 2 = 100ma/div figure 6. scope photo of the v com instantaneous peak current
ad8565/ad8566/ad8567 e11e rev. c 14-lead thin shrink small outline package [tssop] (ru-14) dimensions shown in millimeters 4.50 4.40 4.30 14 8 7 1 6.40 bsc pin 1 5.10 5.00 4.90 0.65 bsc seating plane 0.15 0.05 0.30 0.19 1.20 max 1.05 1.00 0.80 0.20 0.09 8 0 0.75 0.60 0.45 compliant to jedec standards mo-153ab-1 coplanarity 0.10 outline dimensions 5-lead thin shrink small outline transistor package [sc70] (ks-5) dimensions shown in millimeters 0.30 0.15 1.00 0.90 0.70 seating plane 1.10 max 0.22 0.08 0.46 0.36 0.26 3 5 4 1 2 2.00 bsc pin 1 2.10 bsc 0.65 bsc 1.25 bsc 0.10 max 0.10 coplanarity compliant to jedec standards mo-203aa 8-lead micro small outline package [msop] (rm-8) dimensions shown in millimeters 0.80 0.60 0.40 8 0 85 4 1 4.90 bsc pin 1 0.65 bsc 3.00 bsc seating plane 0.15 0.00 0.38 0.22 1.10 max 3.00 bsc coplanarity 0.10 0.23 0.08 compliant to jedec standards mo-187aa
e12e c01909e0e3/04(c) rev. c e12e ad8565/ad8566/ad8567 revision history location page 3/04?data sheet changed from rev. b to rev. c. changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 changes to tpc 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 changes to tpc 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 changes to tpc 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 changes to tpc 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 12/03?data sheet changed from rev. a to rev. b. updated ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 10/01?data sheet changed from rev. 0 to rev. a. edit to 16-lead csp and 5-lead sc70 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edit to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 16-lead lead frame chip scale package [lfcsp] 4 mm 4 mm body (cp-16) dimensions shown in millimeters 16 5 13 8 9 12 1 4 bottom view 2.25 2.10 1.95 0.75 0.60 0.50 0.65 bsc 1.95 bsc 0.35 0.28 0.25 12 max 0.20 ref seating plane pin 1 indicator top view 4.0 bsc sq 3.75 bsc sq 0.60 max 0.60 max 0.05 max 0.02 nom 0.80 max 0.65 typ pin 1 indicator 1.00 0.85 0.80 coplanarity 0.08 sq 0.25 min compliant to jedec standards mo-220-vggc outline dimensions

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